Recently, various electrical products with a display function are increasing in the market. The image transmitting and receiving between each electrical product should be processed by an image processor for showing on the display panel of electrical products. However, the image size and resolution of every electrical product are different, therefore, the scaling device for image scaling has become important.
FIG. 1 shows an image scaling device of the prior art. The device comprises an input multiplexer 11, a line buffer 13, a vertical scaling processor 15, a horizontal scaling processor 17, and an output multiplexer 19. The input multiplexer 11 receives input image data 21 or horizontal size data 26 according to the corresponding scaling signal 22. When the scaling signal 22 is an enlarging signal, it receives the input image data 21; when the scaling signal 22 is a reducing signal, it receives the horizontal size data 26, and the clock is the input clock S_CLK.
Line buffer 13 is used for transferring the input image data 21 from the input multiplexer 11 at the accessing frequency of horizontal size data 26. Further, the clock of the input end of the line buffer 13 is S_CLK, and the clock of the output end thereof is D_CLK. The vertical scaling processor 15 processes the vertical image scaling for the input image data 21 from line buffer 13 or the horizontal size signal 26 according to the corresponding vertical control signal 24 of the scaling signal 22, and outputs a vertical size data 27. The clock is the output clock D_CLK.
Horizontal scaling processor 17 processes the horizontal image scaling for the input image data 21 or vertical size data 27 according to the corresponding horizontal control signal 23 of the scaling signal 22. The horizontal scaling processor 17 comprises two clocks, one of two clocks being selected depending on the scaling signal 22 for operation. When the scaling signal 22 is the enlarging signal, the clock of horizontal scaling processor 17 is D_CLK. When the scaling signal 22 is the reducing signal, the clock of horizontal scaling processor is S_CLK. The output multiplexer 19 outputs an output image data according to the corresponding scaling signal 22, and the clock is output clock D_CLK.
In accordance with the above prior art, integrating the circuits of image enlarging and reducing into a single circuit is too complicated and difficult, especially with the horizontal scaling processor 17 comprising two clocks. When the horizontal image is scaled, the clock control is more difficult for circuit design.
Partial manufacture divides the circuits of image enlarging and reducing into two parts in order to reduce the complication of circuit design as shown in FIG. 2. The upper part is the image data enlarging circuit of the image scaling device, comprising an input multiplexer 111, a line buffer 131, a vertical scaling processor 151, a horizontal scaling processor 171, and an output multiplexer 191. The lower part is the image reducing circuit of the image scaling device, comprising a horizontal scaling processor 172, an input multiplexer 112, a line buffer 132, vertical scaling processor 152, and an output multiplexer 192. This method processes the image enlarging and reducing by two independent circuits, which reduces the difficulty of circuit design, but the redundancy of elements is increased and is around double the number of circuits shown in FIG. 1, so that the cost of hardware is higher.